VLSI Lab 0 - Introduction of Altera FPGA Development Board DE1-SoC (Cyclone 5)

Intel (Altera) Terasic DE1-SoC Development Board (Cyclone V)

For the development board of Terasic development board DE1-SoC using Inter's (Altera) Cyclone V (28nm SoC 5CSEMA5F31C6N),

With ARM Cotex-A9 main processor, below are some tutorials for your references:

Tutorial 1a:

Get started with Altera FPGA SoC and Linux Yocto on Terasic DE1-SoC dev board

Objectives: To learn how to configure HPS, add it into your FPGA project and establish communication between HPS and FPGA.

Procedures:

1) Create a new project and select your device (Cyclone V, 5CSEMA5F31)

2) Import the pin assignment

3) Open Qsyst and add HPS, other peripherals

4) Configure HPS

5) Add HPS components into your FPGA design - Dont forget to execute the TCL files

6) Create HPS header file by executing the "generate" file

7) Write your program and compile it using a makefile

8) Assign IP address to your dev board DE1-SOC

9) Transfer and run it. Have fun.

Reference project files: They are saved in Github:

If you failed to find the files, please feel free to email me: hmp005 (at) gmail.com

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Tutorial 1b:

LEDs blinking on Terasic DE1-SoC dev board (Altera Cyclone V)

Objectives: To learn how to configure HPS, add it into your FPGA project and establish communication between HPS and FPGA.

Reference project files:

References: (for your interest / further studies)

2) More info about the software to be used:

Please note that the newest version software doesn't include ModelSim which is highly useful in VHDL / Verilog simulations in the EDA field.
Quartus Software is not free but the Lite edition is free.
Follow the steps in the website to install Quartus Lite.

3) Introduction about the development board DE1-SoC\

VLSI Design FPGA ASIC Verilog VHDL