VLSI Lab 4 Verilog MegaWizard IP Generator (Compiled on Quartus II v20.1) - 2024 simplified version

 

VLSI Lab 4, EIE, 2024 version


Laboratory Objectives

The objectives of this laboratory are:

·        Understand the use of Altera’s MegaWizard IP generator: (https://ftp.intel.com/Public/Pub/fpgaup/pub/Teaching_Materials/current/Tutorials/Verilog/Using_Library_Modules.pdf)

·        How to specify synthesis options and their impact

·        Understand the impact of placement on the design quality using Pin Planner

Project files are archieved in Google drive:


Top entry sqrt.v file:

// ----- EIE Lab 4
// -----     https://vlsiorfpgadesign.blogspot.com/     ----- //
// Using IP core altsyncram
module sqrt (
sqrt_in, 
sqrt_out);
parameter width = 4;  // # bits
input [width-1:0] sqrt_in;
output [width:0] sqrt_out;
wire [width/2-1:0] q_sig;    // quotient
wire [width/2:0] remainder_sig; // rmainder
sqrt_ip U1_sqrt_inst (
     .radical(sqrt_in),
     .q(q_sig),
      .remainder(remainder_sig));

assign sqrt_out = {q_sig[width/2-1:0], remainder_sig[width/2:0]};
endmodule

// -------------------------------------- // 

Simulation results:




(Click to enlarge the picture)






留言

張貼留言

這個網誌中的熱門文章

VLSI Lab 5 - VGA Controller (Compiled & working on Quartus v20.1)

圖片
VLSI Lab 5 - VGA Controller  (To be compiled on Quartus v20.1) Figure 1 VGA Controller Block Diagram (Click to enlarge) (Source: http://eewiki.net/pages/viewpage.action?pageId=15925278 ) Student is advised to refer to the schematic circuit daigram of the development board DE1-SoC. The onboard video chip DAC is ADV7123 (U5) which can output VGA signals to the VGA output connector (J9). Running PolyU remote-desktop access UDS:  https://puuds.polyu.edu.hk/uds/page/login Please check the availability of the lab:  https://www.eie.polyu.edu.hk/it/lab/cf502/ Datasheet file of Video DAC:  https://www.analog.com/media/en/technical-documentation/data-sheets/adv7123.pdf You could understand the principle from the above website of eewiki. (extracted diagram from the user manual of DE1-SoC) VGA Signal Timing Diagram Pin assignment of the I/Os to connect to control the video DAC chip: Files: 1) Design Verilog file VGA1_V.v :  https://drive.google.com/file/d/1XA12FW6gY...
閱讀完整內容

VLSI Lab 0 - Introduction of Altera FPGA Development Board DE1-SoC (Cyclone 5)

圖片
Intel (Altera) Terasic DE1-SoC Development Board (Cyclone V)    Video: https://youtu.be/sKhvMhTiuM4 For the development board of Terasic development board DE1-SoC using Inter's (Altera) Cyclone V (28nm SoC 5CSEMA5F31C6N),  With ARM Cotex-A9 main processor, below are some tutorials for your references:  Tutorial 1a: Get started with Altera FPGA SoC and Linux Yocto on Terasic DE1-SoC dev board   Objectives: To learn how to configure HPS, add it into your FPGA project and establish communication between HPS and FPGA.  Procedures:  1) Create a new project and select your device (Cyclone V, 5CSEMA5F31)  2) Import the pin assignment  3) Open Qsyst and add HPS, other peripherals  4) Configure HPS  5) Add HPS components into your FPGA design - Dont forget to execute the TCL files  6) Create HPS header file by executing the "generate" file  7) Write your program and compile it using a makefile  8) Assign IP address to yo...
閱讀完整內容