VLSI Design FPGA ASIC Verilog VHDL

VLSI Lab 5 - VGA Controller  (To be compiled on Quartus v20.1) Figure 1 VGA Controller Block Diagram (Click to enlarge) (Source: http://eewiki.net/pages/viewpage.action?pageId=15925278 ) Student is advised to refer to the schematic circuit daigram of the development board DE1-SoC. The onboard video chip DAC is ADV7123 (U5) which can output VGA signals to the VGA output connector (J9). Running PolyU remote-desktop access UDS:  https://puuds.polyu.edu.hk/uds/page/login Please check the availability of the lab:  https://www.eie.polyu.edu.hk/it/lab/cf502/ Datasheet file of Video DAC:  https://www.analog.com/media/en/technical-documentation/data-sheets/adv7123.pdf You could understand the principle from the above website of eewiki. (extracted diagram from the user manual of DE1-SoC) VGA Signal Timing Diagram Pin assignment of the I/Os to connect to control the video DAC chip: Files: 1) Design Verilog file VGA1_V.v :  https://drive.google.com/file/d/1XA12FW6gY...

VLSI Lab 4, EIE Laboratory Objectives The objectives of this laboratory are: ·         Understand the use of Altera’s MegaWizard IP generator: ( https://ftp.intel.com/Public/Pub/fpgaup/pub/Teaching_Materials/current/Tutorials/Verilog/Using_Library_Modules.pdf ) ·         How to specify synthesis options and their impact ·         Understand the impact of placement on the design quality using  Pin  Planner Project files are archieved in Google drive:  https://drive.google.com/drive/folders/1HCdlSi3-0b2UOdJ-86M2q64Z-IPnD7PN?usp=sharing Top entry sqrt.v file: // ----- EIE Lab 4 // -----     https://vlsiorfpgadesign.blogspot.com/     ----- // // Using IP core ALTSQRT module sqrt ( sqrt_in,  sqrt_out); parameter width = 4;  // # bits input [width-1:0] sqrt_in; output [width:0] sqrt_out; wire [width/2-1...

  VLSI Lab 3 This article is to present a Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector is also provided for simulation below.  Lab learning objectives: • Learn to create FSM in Verilog • Use File IO in testbench • User the debugger to display internal signals • Synthesis options using o GUI o Synthesis directives The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes high only when a "1011" sequence is detected. For a state diagram of the Moore FSM for the sequence detector, you might refer to the website at this hyperlink:  https://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequence-detector.html You can also find some similar verilog files of the lab are placed in the Google Drive (hyperlink below), for reference: (you can just download the Quartus files) https://drive.google.com/drive/folders/1ARnWCZSUym3DMnA0rp0RT7bdNTfso2CN?usp=sharing ...